1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a data input circuit that receives a plurality of write data sets supplied in serial and outputs the write data sets to a plurality of data buses in parallel.
2. Description of Related Art
A DRAM (Dynamic Random Access Memory), which is one of typical semiconductor memory devices, generally has a DLL (Delay Locked Loop) circuit to accurately transfer data at high speed between the DRAM and a memory controller. The DLL circuit generates an internal clock signal that is phase-controlled with respect to an external clock signal supplied from the memory controller. The internal clock signal is used as a timing signal to output read data. Therefore, it is possible to accurately transfer data between the DRAM and the memory controller at high speed.
However, the DLL circuit consumes a relatively large amount of power. In a semiconductor memory device that is required so have low power consumption particularly for use in mobile devices, the DLL circuit may not be provided. In such a semiconductor memory device, not only a parallel-to-serial conversion of read data has been performed by using the internal, clock, signal that is not phase-controlled, but also the read data are output to an outside without being phase-controlled. Even during a writing operation, write data that are supplied in synchronism with a data strobe signal are converted from serial to parallel by using the internal clock signal that is not phase-controlled (See Japanese Patent Application Laid-Open No. 2011-108300).
For the parallel-to-serial conversion and the serial-to-parallel conversion, a plurality of frequency-divided clock signals are used. The frequency-divided clock signals are generated by dividing the frequency of an external clock signal, and are different in phase from one another. The frequency-divided clock signals are combined by a multiplier circuit to regenerate an internal clock signal that has the same frequency as the external clock signal. The parallel-to-serial conversion and the serial-to-parallel conversion are performed by using the regenerated internal clock signal. One example of a frequency dividing circuit, as well as of a multiplier circuit, is described in Japanese Patent Application Laid-Open No 2000-273103. The reason why the frequency dividing process and the multiplication process are performed is because, when the internal clock signal having a high-frequency is transmitted via a clock line having long wiring distance, the quality of the internal clock signal decreases due to parasitic capacitance components that the clock line has.
However, in order to transmit a plurality of frequency-divided clock signals via clock lines having long wiring distance, a plurality of drivers having high driving capability need to operate, resulting in consumption of a relatively large amount of power. It is desirable to reduce the transmission of frequency-divided clock signals as much as possible, thereby reducing power consumption. The same is required not only for semiconductor memory devices such as DRAM, but also for all semiconductor devices that are designed to regenerate an internal clock signal by multiplying a plurality of frequency-divided clock signals, and input and output data using the regenerated internal clock signal.